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oh didn't notice these shift instructions

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--HG--
extra : convert_revision : svn%3A39bc706e-5318-0410-9160-8a85361fbb7c/trunk%40131
This commit is contained in:
Borja Ferrer 2006-10-26 17:06:30 +00:00
parent 2f9a5a224e
commit 0196df3cc9
2 changed files with 38 additions and 4 deletions
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20
sourcepawn/vm/jit/x86/jit_x86.cpp
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@ -312,29 +312,49 @@ inline void WriteOp_Shl_C_Pri(JitWriter *jit)
{ {
//shl eax, <val> //shl eax, <val>
jit_uint8_t val = (jit_uint8_t)jit->read_cell(); jit_uint8_t val = (jit_uint8_t)jit->read_cell();
if (val == 1)
{
IA32_Shl_Rm_1(jit, AMX_REG_PRI, MOD_REG);
} else {
IA32_Shl_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG); IA32_Shl_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
} }
}
inline void WriteOp_Shl_C_Alt(JitWriter *jit) inline void WriteOp_Shl_C_Alt(JitWriter *jit)
{ {
//shl edx, <val> //shl edx, <val>
jit_uint8_t val = (jit_uint8_t)jit->read_cell(); jit_uint8_t val = (jit_uint8_t)jit->read_cell();
if (val == 1)
{
IA32_Shl_Rm_1(jit, AMX_REG_ALT, MOD_REG);
} else {
IA32_Shl_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG); IA32_Shl_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
} }
}
inline void WriteOp_Shr_C_Pri(JitWriter *jit) inline void WriteOp_Shr_C_Pri(JitWriter *jit)
{ {
//shr eax, <val> //shr eax, <val>
jit_uint8_t val = (jit_uint8_t)jit->read_cell(); jit_uint8_t val = (jit_uint8_t)jit->read_cell();
if (val == 1)
{
IA32_Shr_Rm_1(jit, AMX_REG_PRI, MOD_REG);
} else {
IA32_Shr_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG); IA32_Shr_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
} }
}
inline void WriteOp_Shr_C_Alt(JitWriter *jit) inline void WriteOp_Shr_C_Alt(JitWriter *jit)
{ {
//shr edx, <val> //shr edx, <val>
jit_uint8_t val = (jit_uint8_t)jit->read_cell(); jit_uint8_t val = (jit_uint8_t)jit->read_cell();
if (val == 1)
{
IA32_Shr_Rm_1(jit, AMX_REG_ALT, MOD_REG);
} else {
IA32_Shr_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG); IA32_Shr_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
} }
}
inline void WriteOp_SMul(JitWriter *jit) inline void WriteOp_SMul(JitWriter *jit)
{ {

14
sourcepawn/vm/jit/x86/x86_macros.h
View File

@ -110,7 +110,9 @@
#define IA32_IMUL_REG_RM_1 0x0F // encoding is _2 #define IA32_IMUL_REG_RM_1 0x0F // encoding is _2
#define IA32_IMUL_REG_RM_2 0xAF // encoding is /r #define IA32_IMUL_REG_RM_2 0xAF // encoding is /r
#define IA32_SHR_RM_IMM8 0xC1 // encoding is /5 <ib> #define IA32_SHR_RM_IMM8 0xC1 // encoding is /5 <ib>
#define IA32_SHR_RM_1 0xD1 // encoding is /5
#define IA32_SHL_RM_IMM8 0xC1 // encoding is /4 <ib> #define IA32_SHL_RM_IMM8 0xC1 // encoding is /4 <ib>
#define IA32_SHL_RM_1 0xD1 // encoding is /4
#define IA32_SAR_RM_CL 0xD3 // encoding is /7 #define IA32_SAR_RM_CL 0xD3 // encoding is /7
#define IA32_SHR_RM_CL 0xD3 // encoding is /5 #define IA32_SHR_RM_CL 0xD3 // encoding is /5
#define IA32_SHL_RM_CL 0xD3 // encoding is /4 #define IA32_SHL_RM_CL 0xD3 // encoding is /4
@ -292,6 +294,12 @@ inline void IA32_Shr_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value
jit->write_ubyte(value); jit->write_ubyte(value);
} }
inline void IA32_Shr_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)
{
jit->write_ubyte(IA32_SHR_RM_1);
jit->write_ubyte(ia32_modrm(mode, 5, dest));
}
inline void IA32_Shl_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode) inline void IA32_Shl_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)
{ {
jit->write_ubyte(IA32_SHL_RM_IMM8); jit->write_ubyte(IA32_SHL_RM_IMM8);
@ -299,6 +307,12 @@ inline void IA32_Shl_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value
jit->write_ubyte(value); jit->write_ubyte(value);
} }
inline void IA32_Shl_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)
{
jit->write_ubyte(IA32_SHL_RM_1);
jit->write_ubyte(ia32_modrm(mode, 4, dest));
}
inline void IA32_Sar_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode) inline void IA32_Sar_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)
{ {
jit->write_ubyte(IA32_SAR_RM_IMM8); jit->write_ubyte(IA32_SAR_RM_IMM8);