diff --git a/sourcepawn/vm/jit/x86/jit_x86.cpp b/sourcepawn/vm/jit/x86/jit_x86.cpp
index 3dc39273..a55fb07e 100644
--- a/sourcepawn/vm/jit/x86/jit_x86.cpp
+++ b/sourcepawn/vm/jit/x86/jit_x86.cpp
@@ -312,28 +312,48 @@ inline void WriteOp_Shl_C_Pri(JitWriter *jit)
 {
 	//shl eax, <val>
 	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
-	IA32_Shl_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
+	if (val == 1)
+	{
+		IA32_Shl_Rm_1(jit, AMX_REG_PRI, MOD_REG);
+	} else {
+		IA32_Shl_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
+	}
 }
 
 inline void WriteOp_Shl_C_Alt(JitWriter *jit)
 {
 	//shl edx, <val>
 	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
-	IA32_Shl_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
+	if (val == 1)
+	{
+		IA32_Shl_Rm_1(jit, AMX_REG_ALT, MOD_REG);
+	} else {
+		IA32_Shl_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
+	}
 }
 
 inline void WriteOp_Shr_C_Pri(JitWriter *jit)
 {
 	//shr eax, <val>
 	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
-	IA32_Shr_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
+	if (val == 1)
+	{
+		IA32_Shr_Rm_1(jit, AMX_REG_PRI, MOD_REG);
+	} else {
+		IA32_Shr_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
+	}
 }
 
 inline void WriteOp_Shr_C_Alt(JitWriter *jit)
 {
 	//shr edx, <val>
 	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
-	IA32_Shr_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
+	if (val == 1)
+	{
+		IA32_Shr_Rm_1(jit, AMX_REG_ALT, MOD_REG);
+	} else {
+		IA32_Shr_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
+	}
 }
 
 inline void WriteOp_SMul(JitWriter *jit)
diff --git a/sourcepawn/vm/jit/x86/x86_macros.h b/sourcepawn/vm/jit/x86/x86_macros.h
index 68e13426..a99904e1 100644
--- a/sourcepawn/vm/jit/x86/x86_macros.h
+++ b/sourcepawn/vm/jit/x86/x86_macros.h
@@ -110,7 +110,9 @@
 #define IA32_IMUL_REG_RM_1		0x0F	// encoding is _2
 #define IA32_IMUL_REG_RM_2		0xAF	// encoding is /r
 #define IA32_SHR_RM_IMM8		0xC1	// encoding is /5 <ib>
+#define IA32_SHR_RM_1			0xD1	// encoding is /5
 #define IA32_SHL_RM_IMM8		0xC1	// encoding is /4 <ib>
+#define IA32_SHL_RM_1			0xD1	// encoding is /4
 #define IA32_SAR_RM_CL			0xD3	// encoding is /7
 #define IA32_SHR_RM_CL			0xD3	// encoding is /5
 #define IA32_SHL_RM_CL			0xD3	// encoding is /4
@@ -292,6 +294,12 @@ inline void IA32_Shr_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value
 	jit->write_ubyte(value);
 }
 
+inline void IA32_Shr_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)
+{
+	jit->write_ubyte(IA32_SHR_RM_1);
+	jit->write_ubyte(ia32_modrm(mode, 5, dest));
+}
+
 inline void IA32_Shl_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)
 {
 	jit->write_ubyte(IA32_SHL_RM_IMM8);
@@ -299,6 +307,12 @@ inline void IA32_Shl_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value
 	jit->write_ubyte(value);
 }
 
+inline void IA32_Shl_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)
+{
+	jit->write_ubyte(IA32_SHL_RM_1);
+	jit->write_ubyte(ia32_modrm(mode, 4, dest));
+}
+
 inline void IA32_Sar_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)
 {
 	jit->write_ubyte(IA32_SAR_RM_IMM8);