749177d0b3
--HG-- extra : convert_revision : svn%3A39bc706e-5318-0410-9160-8a85361fbb7c/trunk%402254
326 lines
9.0 KiB
C
326 lines
9.0 KiB
C
/**
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* vim: set ts=4 :
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* =============================================================================
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* SourceMod
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* Copyright (C) 2004-2008 AlliedModders LLC. All rights reserved.
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* =============================================================================
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License, version 3.0, as published by the
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* Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* As a special exception, AlliedModders LLC gives you permission to link the
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* code of this program (as well as its derivative works) to "Half-Life 2," the
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* "Source Engine," the "SourcePawn JIT," and any Game MODs that run on software
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* by the Valve Corporation. You must obey the GNU General Public License in
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* all respects for all other code used. Additionally, AlliedModders LLC grants
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* this exception to all derivative works. AlliedModders LLC defines further
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* exceptions, found in LICENSE.txt (as of this writing, version JULY-31-2007),
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* or <http://www.sourcemod.net/license.php>.
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*
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* Version: $Id$
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*/
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#ifndef _INCLUDE_SOURCEPAWN_JIT_X86_UNGEN_OPCODES_H_
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#define _INCLUDE_SOURCEPAWN_JIT_X86_UNGEN_OPCODES_H_
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inline void WriteOp_UMul(JitWriter *jit)
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{
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//mov ecx, edx
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//mul edx
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//mov edx, ecx
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IA32_Mov_Reg_Rm(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
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IA32_Mul_Rm(jit, AMX_REG_ALT, MOD_REG);
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IA32_Mov_Reg_Rm(jit, AMX_REG_ALT, AMX_REG_TMP, MOD_REG);
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}
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inline void WriteOp_Less(JitWriter *jit)
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{
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//cmp eax, edx ; PRI < ALT ? (unsigned)
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//mov eax, 0
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//setb al
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
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IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_B);
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}
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inline void WriteOp_Leq(JitWriter *jit)
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{
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//cmp eax, edx ; PRI <= ALT ? (unsigned)
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//mov eax, 0
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//setbe al
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
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IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_BE);
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}
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inline void WriteOp_Grtr(JitWriter *jit)
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{
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//cmp eax, edx ; PRI > ALT ? (unsigned)
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//mov eax, 0
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//seta al
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
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IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_A);
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}
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inline void WriteOp_Geq(JitWriter *jit)
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{
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//cmp eax, edx ; PRI >= ALT ? (unsigned)
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//mov eax, 0
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//setae al
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
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IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_AE);
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}
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inline void WriteOp_Align_Pri(JitWriter *jit)
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{
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//xor eax, <cellsize - val>
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cell_t val = sizeof(cell_t) - jit->read_cell();
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if (val <= SCHAR_MAX && val >= SCHAR_MIN)
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{
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IA32_Xor_Rm_Imm8(jit, AMX_REG_PRI, MOD_REG, (jit_int8_t)val);
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} else {
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IA32_Xor_Eax_Imm32(jit, val);
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}
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}
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inline void WriteOp_Align_Alt(JitWriter *jit)
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{
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//xor edx, <cellsize - val>
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cell_t val = sizeof(cell_t) - jit->read_cell();
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if (val <= SCHAR_MAX && val >= SCHAR_MIN)
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{
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IA32_Xor_Rm_Imm8(jit, AMX_REG_ALT, MOD_REG, (jit_int8_t)val);
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} else {
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IA32_Xor_Rm_Imm32(jit, AMX_REG_ALT, MOD_REG, val);
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}
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}
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inline void WriteOp_Cmps(JitWriter *jit)
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{
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//push edi
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//push esi
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//lea esi, [ebp+edx]
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//lea edi, [ebp+eax]
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//mov ecx, <val>
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unsigned int val = jit->read_cell();
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IA32_Push_Reg(jit, REG_EDI);
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IA32_Push_Reg(jit, REG_ESI);
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IA32_Lea_Reg_DispEBPRegMult(jit, REG_ESI, AMX_REG_DAT, AMX_REG_ALT, NOSCALE);
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IA32_Lea_Reg_DispEBPRegMult(jit, REG_EDI, AMX_REG_DAT, AMX_REG_PRI, NOSCALE);
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IA32_Mov_Reg_Imm32(jit, REG_ECX, val);
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//xor eax, eax
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//repe cmpsb
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//je :cmps1
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IA32_Xor_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_PRI, MOD_REG);
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IA32_Rep(jit);
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IA32_Cmpsb(jit);
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jitoffs_t jmp = IA32_Jump_Cond_Imm8(jit, CC_E, 0);
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//sbb eax, eax
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//sbb eax, -1
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IA32_Sbb_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_PRI, MOD_REG);
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IA32_Sbb_Rm_Imm8(jit, AMX_REG_PRI, -1, MOD_REG);
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//:cmps1
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//pop esi
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//pop edi
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IA32_Send_Jump8_Here(jit, jmp);
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IA32_Pop_Reg(jit, REG_ESI);
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IA32_Pop_Reg(jit, REG_EDI);
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}
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inline void WriteOp_Lctrl(JitWriter *jit)
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{
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cell_t val = jit->read_cell();
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switch (val)
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{
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case 0:
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{
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//mov ecx, [esi+ctx]
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//mov eax, [ecx+ctx.codebase]
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_CONTEXT);
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_TMP, offsetof(sp_context_t, codebase));
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break;
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}
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case 1:
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{
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//mov eax, ebp
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IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_DAT, MOD_REG);
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break;
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}
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case 2:
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{
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//mov eax, [esi+hea]
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_INFO, AMX_INFO_HEAP);
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break;
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}
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case 3:
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{
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//mov ecx, [esi+ctx]
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//mov eax, [ecx+ctx.memory]
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_CONTEXT);
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_TMP, offsetof(sp_context_t, memory));
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break;
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}
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case 4:
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{
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//mov eax, edi
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//sub eax, ebp - unrelocate
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IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_STK, MOD_REG);
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IA32_Sub_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_DAT, MOD_REG);
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break;
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}
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case 5:
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{
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//mov eax, [esi+frm]
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IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_INFO, MOD_MEM_REG);
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break;
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}
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case 6:
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{
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//mov eax, [cip]
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jitoffs_t imm32 = IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
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jitoffs_t save = jit->get_outputpos();
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jit->set_outputpos(imm32);
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jit->write_int32((uint32_t)(jit->outbase + save));
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jit->set_outputpos(save);
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break;
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}
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}
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}
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inline void WriteOp_Sctrl(JitWriter *jit)
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{
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cell_t val = jit->read_cell();
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switch (val)
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{
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case 2:
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{
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//mov [esi+hea], eax
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IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, AMX_REG_PRI, AMX_INFO_HEAP);
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break;
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}
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case 4:
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{
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//lea edi, [ebp+eax]
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IA32_Lea_Reg_DispEBPRegMult(jit, AMX_REG_STK, AMX_REG_DAT, AMX_REG_PRI, NOSCALE);
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break;
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}
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case 5:
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{
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//lea ebx, [ebp+eax] - overwrite frm
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//mov [esi+frm], eax - overwrite stacked frame
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IA32_Lea_Reg_DispEBPRegMult(jit, AMX_REG_FRM, AMX_REG_DAT, AMX_REG_PRI, NOSCALE);
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IA32_Mov_Rm_Reg(jit, AMX_REG_INFO, AMX_REG_PRI, MOD_MEM_REG);
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break;
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}
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case 6:
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{
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IA32_Jump_Reg(jit, AMX_REG_PRI);
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break;
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}
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}
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}
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inline void WriteOp_UDiv(JitWriter *jit)
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{
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//mov ecx, edx
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//xor edx, edx
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//div ecx
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IA32_Mov_Reg_Rm(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
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IA32_Xor_Reg_Rm(jit, AMX_REG_ALT, AMX_REG_ALT, MOD_REG);
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Write_Check_DivZero(jit, AMX_REG_TMP);
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IA32_Div_Rm(jit, AMX_REG_TMP, MOD_REG);
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}
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inline void WriteOp_UDiv_Alt(JitWriter *jit)
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{
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//mov ecx, eax
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//mov eax, edx
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//xor edx, edx
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//div ecx
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IA32_Mov_Reg_Rm(jit, AMX_REG_TMP, AMX_REG_PRI, MOD_REG);
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IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Xor_Reg_Rm(jit, AMX_REG_ALT, AMX_REG_ALT, MOD_REG);
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Write_Check_DivZero(jit, AMX_REG_TMP);
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IA32_Div_Rm(jit, AMX_REG_TMP, MOD_REG);
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}
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inline void WriteOp_Ret(JitWriter *jit)
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{
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//mov ebx, [edi] - get old FRM
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//add edi, 4 - pop stack
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//mov [esi+frm], ebx - restore
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//add ebx, ebp - relocate
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//ret
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IA32_Mov_Reg_Rm(jit, AMX_REG_FRM, AMX_REG_STK, MOD_MEM_REG);
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IA32_Add_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
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IA32_Mov_Rm_Reg(jit, AMX_REG_INFO, AMX_REG_FRM, MOD_MEM_REG);
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IA32_Add_Reg_Rm(jit, AMX_REG_FRM, AMX_REG_DAT, MOD_REG);
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IA32_Return(jit);
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}
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inline void WriteOp_JRel(JitWriter *jit)
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{
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//jmp <offs> ;relative jump
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cell_t cip_offs = jit->read_cell();
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/* Note that since code size calculation has to be done in the same
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* phase as building relocation information, we cannot know the jump size
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* beforehand. Thus, we always write full 32bit jumps for safety.
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*/
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jitoffs_t jmp = IA32_Jump_Imm32(jit, 0);
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IA32_Write_Jump32(jit, jmp, RelocLookup(jit, cip_offs));
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}
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inline void WriteOp_Jless(JitWriter *jit)
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{
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//cmp eax, edx
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//jb <target>
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cell_t target = jit->read_cell();
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Jump_Cond_Imm32(jit, CC_B, RelocLookup(jit, target, false));
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}
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inline void WriteOp_Jleq(JitWriter *jit)
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{
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//cmp eax, edx
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//jbe <target>
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cell_t target = jit->read_cell();
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Jump_Cond_Imm32(jit, CC_BE, RelocLookup(jit, target, false));
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}
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inline void WriteOp_Jgrtr(JitWriter *jit)
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{
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//cmp eax, edx
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//ja <target>
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cell_t target = jit->read_cell();
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Jump_Cond_Imm32(jit, CC_A, RelocLookup(jit, target, false));
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}
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inline void WriteOp_Jgeq(JitWriter *jit)
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{
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//cmp eax, edx
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//jae <target>
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cell_t target = jit->read_cell();
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IA32_Cmp_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
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IA32_Jump_Cond_Imm32(jit, CC_AE, RelocLookup(jit, target, false));
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}
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#endif //_INCLUDE_SOURCEPAWN_JIT_X86_UNGEN_OPCODES_H_
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