Use SSE when available for floating-point operations (bug 5841, r=her).

2013-08-08 20:26:36 -07:00
parent f031ad23f6
commit bf325b72f1
7 changed files with 339 additions and 41 deletions
@@ -0,0 +1,33 @@
+/**
+ * vim: set ts=8 sts=2 sw=2 tw=99 et:
+ * =============================================================================
+ * SourcePawn JIT SDK
+ * Copyright (C) 2004-2008 AlliedModders LLC.  All rights reserved.
+ * =============================================================================
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License, version 3.0, as published by the
+ * Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As a special exception, AlliedModders LLC gives you permission to link the
+ * code of this program (as well as its derivative works) to "Half-Life 2," the
+ * "Source Engine," the "SourcePawn JIT," and any Game MODs that run on software
+ * by the Valve Corporation.  You must obey the GNU General Public License in
+ * all respects for all other code used.  Additionally, AlliedModders LLC grants
+ * this exception to all derivative works.  AlliedModders LLC defines further
+ * exceptions, found in LICENSE.txt (as of this writing, version JULY-31-2007),
+ * or <http://www.sourcemod.net/license.php>.
+ *
+ * Version: $Id$
+ */
+#include <assembler-x86.h>
+
+CPUFeatures AssemblerX86::X86Features;
@@ -94,6 +94,25 @@ struct FloatRegister
  }
 };

+struct CPUFeatures
+{
+  CPUFeatures()
+  {
+    memset(this, 0, sizeof(*this));
+  }
+
+  bool fpu;
+  bool mmx;
+  bool sse;
+  bool sse2;
+  bool sse3;
+  bool ssse3;
+  bool sse4_1;
+  bool sse4_2;
+  bool avx;
+  bool avx2;
+};
+
 const Register eax = { 0 };
 const Register ecx = { 1 };
 const Register edx = { 2 };
@@ -299,7 +318,19 @@ struct Operand

 class AssemblerX86 : public Assembler
 {
+ private:
+  // List of processor features; to be used, this must be filled in at
+  // startup.
+  static CPUFeatures X86Features; 
+
 public:
+  static void SetFeatures(const CPUFeatures &features) {
+    X86Features = features;
+  }
+  static const CPUFeatures &Features() {
+    return X86Features;
+  }
+
  void movl(Register dest, Register src) {
    emit1(0x89, src.code, dest.code);
  }
@@ -712,6 +743,74 @@ class AssemblerX86 : public Assembler
      outOfMemory_ = true;
  }

+  void cpuid() {
+    emit2(0x0f, 0xa2);
+  }
+
+
+  // SSE operations can only be used if the feature detection function has
+  // been run *and* detected the appropriate level of functionality.
+  void movss(FloatRegister dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x10, dest.code, src);
+  }
+  void cvttss2si(Register dest, Register src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x2c, dest.code, src.code);
+  }
+  void cvttss2si(Register dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x2c, dest.code, src);
+  }
+  void cvtss2si(Register dest, Register src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x2d, dest.code, src.code);
+  }
+  void cvtss2si(Register dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x2d, dest.code, src);
+  }
+  void cvtsi2ss(FloatRegister dest, Register src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x2a, dest.code, src.code);
+  }
+  void cvtsi2ss(FloatRegister dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x2a, dest.code, src);
+  }
+  void addss(FloatRegister dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x58, dest.code, src);
+  }
+  void subss(FloatRegister dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x5c, dest.code, src);
+  }
+  void mulss(FloatRegister dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x59, dest.code, src);
+  }
+  void divss(FloatRegister dest, const Operand &src) {
+    assert(Features().sse);
+    emit3(0xf3, 0x0f, 0x5e, dest.code, src);
+  }
+  void ucomiss(FloatRegister left, Register right) {
+    emit2(0x0f, 0x2e, left.code, right.code);
+  }
+  void ucomiss(FloatRegister left, const Operand &right) {
+    emit2(0x0f, 0x2e, left.code, right);
+  }
+
+  // SSE2-only instructions.
+  void movd(Register dest, FloatRegister src) {
+    assert(Features().sse2);
+    emit3(0x66, 0x0f, 0x7e, dest.code, src.code);
+  }
+  void movd(Register dest, const Operand &src) {
+    assert(Features().sse2);
+    emit3(0x66, 0x0f, 0x7e, dest.code, src);
+  }
+
  static void PatchRel32Absolute(uint8_t *ip, void *ptr) {
    int32_t delta = uint32_t(ptr) - uint32_t(ip);
    *reinterpret_cast<int32_t *>(ip - 4) = delta;
@@ -806,6 +905,22 @@ class AssemblerX86 : public Assembler
    emit(reg, operand);
  }

+  void emit3(uint8_t prefix1, uint8_t prefix2, uint8_t opcode) {
+    ensureSpace();
+    *pos_++ = prefix1;
+    *pos_++ = prefix2;
+    *pos_++ = opcode;
+  }
+  void emit3(uint8_t prefix1, uint8_t prefix2, uint8_t opcode, uint8_t reg, uint8_t opreg) {
+    emit3(prefix1, prefix2, opcode);
+    assert(reg <= 7);
+    *pos_++ = (kModeReg << 6) | (reg << 3) | opreg;
+  }
+  void emit3(uint8_t prefix1, uint8_t prefix2, uint8_t opcode, uint8_t reg, const Operand &operand) {
+    emit3(prefix1, prefix2, opcode);
+    emit(reg, operand);
+  }
+
  template <typename T>
  void shift_cl(const T &t, uint8_t r) {
    emit1(0xd3, r, t);
@@ -0,0 +1,104 @@
+/**
+ * vim: set ts=8 sts=2 sw=2 tw=99 et:
+ * =============================================================================
+ * SourcePawn JIT SDK
+ * Copyright (C) 2004-2008 AlliedModders LLC.  All rights reserved.
+ * =============================================================================
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License, version 3.0, as published by the
+ * Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * As a special exception, AlliedModders LLC gives you permission to link the
+ * code of this program (as well as its derivative works) to "Half-Life 2," the
+ * "Source Engine," the "SourcePawn JIT," and any Game MODs that run on software
+ * by the Valve Corporation.  You must obey the GNU General Public License in
+ * all respects for all other code used.  Additionally, AlliedModders LLC grants
+ * this exception to all derivative works.  AlliedModders LLC defines further
+ * exceptions, found in LICENSE.txt (as of this writing, version JULY-31-2007),
+ * or <http://www.sourcemod.net/license.php>.
+ *
+ * Version: $Id$
+ */
+#ifndef _include_sourcepawn_macroassembler_x86h__
+#define _include_sourcepawn_macroassembler_x86h__
+
+#include <assembler.h>
+#include <ke_vector.h>
+#include <string.h>
+#include <assembler-x86.h>
+
+class MacroAssemblerX86 : public AssemblerX86
+{
+  public:
+    static void GenerateFeatureDetection(MacroAssemblerX86 &masm) {
+      masm.push(ebp);
+      masm.movl(ebp, esp);
+      masm.push(ebx);
+      {
+        // Get ECX, EDX feature bits at the first CPUID level.
+        masm.movl(eax, 1);
+        masm.cpuid();
+        masm.movl(eax, Operand(ebp, 8));
+        masm.movl(Operand(eax, 0), ecx);
+        masm.movl(eax, Operand(ebp, 12));
+        masm.movl(Operand(eax, 0), edx);
+      }
+
+      // Zero out bits we're not guaranteed to get.
+      masm.movl(eax, Operand(ebp, 16));
+      masm.movl(Operand(eax, 0), 0);
+
+      Label skip_level_7;
+      {
+        // Get EBX feature bits at 7th CPUID level.
+        masm.movl(eax, 0);
+        masm.cpuid();
+        masm.cmpl(eax, 7);
+        masm.j(below, &skip_level_7);
+        masm.movl(eax, 7);
+        masm.movl(ecx, 0);
+        masm.cpuid();
+        masm.movl(eax, Operand(ebp, 16));
+        masm.movl(Operand(eax, 0), ebx);
+      }
+      masm.bind(&skip_level_7);
+
+      masm.pop(ebx);
+      masm.pop(ebp);
+      masm.ret();
+    }
+
+    static void RunFeatureDetection(void *code) {
+      typedef void (*fn_t)(int *reg_ecx, int *reg_edx, int *reg_ebx);
+
+      int reg_ecx, reg_edx, reg_ebx;
+      ((fn_t)code)(&reg_ecx, &reg_edx, &reg_ebx);
+      
+      CPUFeatures features;
+      features.fpu = !!(reg_edx & (1 << 0));
+      features.mmx = !!(reg_edx & (1 << 23));
+      features.sse = !!(reg_edx & (1 << 25));
+      features.sse2 = !!(reg_edx & (1 << 26));
+      features.sse3 = !!(reg_ecx & (1 << 0));
+      features.ssse3 = !!(reg_ecx & (1 << 9));
+      features.sse4_1 = !!(reg_ecx & (1 << 19));
+      features.sse4_2 = !!(reg_ecx & (1 << 20));
+      features.avx = !!(reg_ecx & (1 << 28));
+      features.avx2 = !!(reg_ebx & (1 << 5));
+      SetFeatures(features);
+    }
+
+  private:
+};
+
+#endif // _include_sourcepawn_macroassembler_x86h__
+