Added new op.genarray for dynamic arrays
Fixed up opcode table for new opcodes --HG-- extra : convert_revision : svn%3A39bc706e-5318-0410-9160-8a85361fbb7c/trunk%40125
This commit is contained in:
David Anderson
parent
a19823e4c6
commit
209dd31751
@ -960,15 +960,55 @@ inline void WriteOp_Fill(JitWriter *jit)
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IA32_Pop_Reg(jit, REG_EDI);
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}
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inline void WriteOp_Heap_Pri(JitWriter *jit)
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inline void WriteOp_Heap_I(JitWriter *jit)
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{
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//mov edx, [esi+hea]
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//add [esi+hea], eax
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_INFO, AMX_INFO_HEAP);
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IA32_Add_Rm_Reg_Disp8(jit, AMX_REG_INFO, AMX_REG_PRI, AMX_INFO_HEAP);
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//sub [esi+hea], 4
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//mov ecx, [esi+hea]
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//mov ecx, [ebp+ecx]
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//sub [esi+hea], ecx
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IA32_Sub_Rm_Imm8_Disp8(jit, AMX_REG_INFO, 4, AMX_INFO_HEAP);
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_HEAP);
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IA32_Mov_Reg_RmEBP_Disp_Reg(jit, AMX_REG_TMP, AMX_REG_DAT, AMX_REG_TMP, NOSCALE);
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IA32_Add_Rm_Reg_Disp8(jit, AMX_REG_INFO, AMX_REG_TMP, AMX_INFO_HEAP);
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/* :TODO: should we do a full bounds check here? */
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Write_CheckHeap_Min(jit);
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Write_CheckHeap_Low(jit);
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}
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inline void WriteOp_GenArray(JitWriter *jit)
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{
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cell_t val = jit->read_cell();
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if (val == 1)
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{
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/* flat array. we can generate this without indirection tables. */
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/* Note that we can overwrite ALT because technically STACK should be destroying ALT */
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//mov edx, [esi+info.heap]
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//mov ecx, [edi]
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//mov [edi], edx ;store base of array into stack
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//lea edx, [edx+ecx*4+4] ;get the final new heap pointer
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//mov [esi+info.heap], edx ;store heap pointer back
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//add edx, ebp ;relocate
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//cmp edx, edi ;compare against stack pointer
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//jae :error ;error out if not enough space
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//shl ecx, 2
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//mov [edx-4], ecx ;store # of cells allocated
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_INFO, AMX_INFO_HEAP);
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IA32_Mov_Reg_Rm(jit, AMX_REG_TMP, AMX_REG_STK, MOD_MEM_REG);
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IA32_Mov_Rm_Reg(jit, AMX_REG_STK, AMX_REG_ALT, MOD_MEM_REG);
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IA32_Lea_Reg_DispRegMultImm8(jit, AMX_REG_ALT, AMX_REG_ALT, AMX_REG_TMP, SCALE4, 4);
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IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, AMX_REG_ALT, AMX_INFO_HEAP);
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IA32_Add_Rm_Reg(jit, AMX_REG_ALT, AMX_REG_DAT, MOD_REG);
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IA32_Cmp_Rm_Reg(jit, AMX_REG_ALT, AMX_REG_STK, MOD_REG);
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IA32_Jump_Cond_Imm32_Abs(jit, CC_AE, ((CompData *)jit->data)->jit_error_heaplow);
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IA32_Shl_Rm_Imm8(jit, AMX_REG_TMP, 4, MOD_REG);
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IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_ALT, AMX_REG_TMP, -4);
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} else {
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//mov ecx, num_dims
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//call [genarray]
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IA32_Mov_Reg_Imm32(jit, AMX_REG_TMP, val);
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jitoffs_t call = IA32_Call_Imm32(jit, 0);
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IA32_Write_Jump32(jit, call, ((CompData *)jit->data)->jit_genarray);
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}
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}
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inline void WriteOp_Push_Heap_C(JitWriter *jit)
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@ -984,18 +1024,6 @@ inline void WriteOp_Push_Heap_C(JitWriter *jit)
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Write_CheckHeap_Low(jit);
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}
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inline void WriteOp_Pop_Heap_Pri(JitWriter *jit)
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{
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//sub [esi+hea], 4
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//mov ecx, [esi+hea]
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//mov eax, [ebp+ecx]
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IA32_Sub_Rm_Imm8_Disp8(jit, AMX_REG_INFO, 4, AMX_INFO_HEAP);
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IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_HEAP);
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IA32_Mov_Reg_RmEBP_Disp_Reg(jit, AMX_REG_PRI, AMX_REG_DAT, AMX_REG_TMP, NOSCALE);
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Write_CheckHeap_Min(jit);
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}
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inline void WriteOp_Load_Both(JitWriter *jit)
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{
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WriteOp_Load_Pri(jit);
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@ -27,6 +27,7 @@ public:
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jitoffs_t jit_verify_addr_edx;
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jitoffs_t jit_break; /* call to op.break */
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jitoffs_t jit_sysreq_n; /* call version of op.sysreq.n */
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jitoffs_t jit_genarray; /* call to genarray intrinsic */
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jitoffs_t jit_error_bounds;
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jitoffs_t jit_error_divzero;
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jitoffs_t jit_error_stacklow;
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@ -451,6 +451,10 @@ void WriteOp_Sysreq_C_Function(JitWriter *jit)
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IA32_Return(jit);
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}
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void WriteIntrinsic_GenArray(JitWriter *jit)
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{
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}
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void WriteOp_Sysreq_N_Function(JitWriter *jit)
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{
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/* The big daddy of opcodes.
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@ -16,6 +16,11 @@ jitoffs_t Write_Execute_Function(JitWriter *jit);
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void WriteOp_Sysreq_N_Function(JitWriter *jit);
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void WriteOp_Sysreq_C_Function(JitWriter *jit);
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/**
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* Write the GENARRAY intrinsic function.
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*/
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void WriteIntrinsic_GenArray(JitWriter *jit);
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/**
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* Generates code to set an error state in the VM and return.
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* This is used for generating the error set points in the VM.
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@ -240,9 +245,9 @@ typedef enum
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OP_SYSREQ_D, // !GEN UNSUPPORT
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OP_SYSREQ_ND, // !GEN UNSUPPORT
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/* ----- */
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OP_HEAP_PRI, //DONE
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OP_HEAP_I, //
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OP_PUSH_HEAP_C, //DONE
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OP_POP_HEAP_PRI, //DONE
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OP_GENARRAY, //
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/* ----- */
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OP_NUM_OPCODES
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} OPCODE;
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@ -458,21 +458,6 @@
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WriteOp_Fill(jit);
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break;
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}
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case OP_HEAP_PRI:
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{
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WriteOp_Heap_Pri(jit);
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break;
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}
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case OP_PUSH_HEAP_C:
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{
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WriteOp_Push_Heap_C(jit);
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break;
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}
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case OP_POP_HEAP_PRI:
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{
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WriteOp_Pop_Heap_Pri(jit);
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break;
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}
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case OP_PUSH_C:
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{
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WriteOp_Push_C(jit);
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@ -658,6 +643,21 @@
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}
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break;
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}
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case OP_PUSH_HEAP_C:
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{
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WriteOp_Push_Heap_C(jit);
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break;
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}
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case OP_HEAP_I:
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{
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WriteOp_Heap_I(jit);
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break;
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}
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case OP_GENARRAY:
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{
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WriteOp_GenArray(jit);
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break;
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}
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#if defined USE_UNGEN_OPCODES
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#include "ungen_opcode_switch.inc"
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#endif
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@ -82,6 +82,8 @@
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#define IA32_CMP_RM_IMM8 0x83 // encoding is /7 <imm8>
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#define IA32_CMP_AL_IMM32 0x3C // no extra encoding
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#define IA32_CMP_EAX_IMM32 0x3D // no extra encoding
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#define IA32_CMP_RM_REG 0x39 // encoding is /r
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#define IA32_CMP_REG_RM 0x3B // encoding is /r
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#define IA32_CMPSB 0xA6 // no extra encoding
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#define IA32_TEST_RM_REG 0x85 // encoding is /r
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#define IA32_JCC_IMM 0x70 // encoding is +cc <imm8>
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@ -110,8 +112,6 @@
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#define IA32_SHR_RM_CL 0xD3 // encoding is /5
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#define IA32_SHL_RM_CL 0xD3 // encoding is /4
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#define IA32_SAR_RM_IMM8 0xC1 // encoding is /7 <ib>
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#define IA32_CMP_RM_REG 0x39 // encoding is /r
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#define IA32_CMP_REG_RM 0x3B // encoding is /r
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#define IA32_SETCC_RM8_1 0x0F // opcode part 1
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#define IA32_SETCC_RM8_2 0x90 // encoding is +cc /0 (8bits)
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#define IA32_XCHG_EAX_REG 0x90 // encoding is +r
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